Data transfer rates between memory and memory controllers are ever increasing. To improve signal integrity at higher transfer rates, memory buffer devices between the memory devices and memory controllers have been introduced. See, for example, U.S. Pat. No. 6,317,352 xe2x80x9cApparatus for Implementing a Buffered Daisy Chain Connection Between a Memory Controller and Memory Modulesxe2x80x9d. The memory buffer devices reduce the number of devices connected to the memory bus, thus reducing the number of stubs on the memory bus which are a source of signal reflections. Further, memory buffer devices reduce the load on the memory controller by reducing the number of devices being directly driven by the memory controller. By reducing the load, the memory controller may utilize faster signal rates and/or lower signal voltages. The memory buffer devices, however, consume circuit board area. Reducing the circuit board footprint of the memory buffer devices may help satisfy the ever increasing desire for smaller form factors and increased storage capacity.